Programmable Differential Delay Circuit With Fine Delay Adjustment
Abstract
Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.
- Inventors:
-
- Eau Claire, WI
- Chippewa Falls, WI
- Issue Date:
- OSTI Identifier:
- 879633
- Patent Number(s):
- 6417713
- Application Number:
- 09/475466
- Assignee:
- Silicon Graphics, Inc. (Mountain View, CA)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H03 - BASIC ELECTRONIC CIRCUITRY H03K - PULSE TECHNIQUE
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
Citation Formats
DeRyckere, John F, Jenkins, Philip Nord, and Cornett, Frank Nolan. Programmable Differential Delay Circuit With Fine Delay Adjustment. United States: N. p., 2002.
Web.
DeRyckere, John F, Jenkins, Philip Nord, & Cornett, Frank Nolan. Programmable Differential Delay Circuit With Fine Delay Adjustment. United States.
DeRyckere, John F, Jenkins, Philip Nord, and Cornett, Frank Nolan. Tue .
"Programmable Differential Delay Circuit With Fine Delay Adjustment". United States. https://www.osti.gov/servlets/purl/879633.
@article{osti_879633,
title = {Programmable Differential Delay Circuit With Fine Delay Adjustment},
author = {DeRyckere, John F and Jenkins, Philip Nord and Cornett, Frank Nolan},
abstractNote = {Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Jul 09 00:00:00 EDT 2002},
month = {Tue Jul 09 00:00:00 EDT 2002}
}
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