Title: Metal-based passivation-assisted plasma etching of III-v semiconductors

Abstract

According to one embodiment, a method includes performing a plasma etching process on a masked III-V semiconductor, and forming a passivation layer on etched portions of the III-V semiconductor. The passivation layer includes at least one of a group III element and/or a metal from the following: Ni, Cr, W, Mo, Pt, Pd, Mg, Ti, Zr, Hf, Y, Ta, and Sc.

Inventors:

Harrison, Sara Elizabeth; Frye, Clint; Nikolic, Rebecca J.; Shao, Qinghui; Voss, Lars F.

Issue Date:

Tue Sep 28 00:00:00 EDT 2021

Research Org.:

Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)

Sponsoring Org.:

USDOE

OSTI Identifier:

1840499

Patent Number(s):

11133190

Application Number:

15/971,999

Assignee:

Lawrence Livermore National Security, LLC (Livermore, CA)

Patent Classifications (CPCs):

H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

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H - ELECTRICITY H01 - BASIC ELECTRIC ELEMENTS H01L - SEMICONDUCTOR DEVICES

H01L21/02057 - {Cleaning during device manufacture}
H01L21/02178 - {the material containing aluminium, e.g. Al2O3}
H01L21/02241 - {III-V semiconductor}
H01L21/02274 - {in the presence of a plasma [PECVD]}
H01L21/30621 - {Vapour phase etching}
H01L21/308 - using masks
H01L21/3081 - {characterised by their composition, e.g. multilayer masks, materials}

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DOE Contract Number:  

AC52-07NA27344

Resource Type:

Patent

Resource Relation:

Patent File Date: 05/04/2018

Country of Publication:

United States

Language:

English