Extensible packet processing architecture
Abstract
A technique for distributed packet processing includes sequentially passing packets associated with packet flows between a plurality of processing engines along a flow through data bus linking the plurality of processing engines in series. At least one packet within a given packet flow is marked by a given processing engine to signify by the given processing engine to the other processing engines that the given processing engine has claimed the given packet flow for processing. A processing function is applied to each of the packet flows within the processing engines and the processed packets are output on a time-shared, arbitered data bus coupled to the plurality of processing engines.
- Inventors:
- Issue Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1093265
- Patent Number(s):
- 8514855
- Application Number:
- 12/773,120
- Assignee:
- Sandia Corporation (Albuquerque, NM)
- Patent Classifications (CPCs):
-
H - ELECTRICITY H04 - ELECTRIC COMMUNICATION TECHNIQUE H04L - TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- DOE Contract Number:
- AC04-94AL85000
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Robertson, Perry J., Hamlet, Jason R., Pierson, Lyndon G., Olsberg, Ronald R., and Chun, Guy D. Extensible packet processing architecture. United States: N. p., 2013.
Web.
Robertson, Perry J., Hamlet, Jason R., Pierson, Lyndon G., Olsberg, Ronald R., & Chun, Guy D. Extensible packet processing architecture. United States.
Robertson, Perry J., Hamlet, Jason R., Pierson, Lyndon G., Olsberg, Ronald R., and Chun, Guy D. Tue .
"Extensible packet processing architecture". United States. https://www.osti.gov/servlets/purl/1093265.
@article{osti_1093265,
title = {Extensible packet processing architecture},
author = {Robertson, Perry J. and Hamlet, Jason R. and Pierson, Lyndon G. and Olsberg, Ronald R. and Chun, Guy D.},
abstractNote = {A technique for distributed packet processing includes sequentially passing packets associated with packet flows between a plurality of processing engines along a flow through data bus linking the plurality of processing engines in series. At least one packet within a given packet flow is marked by a given processing engine to signify by the given processing engine to the other processing engines that the given processing engine has claimed the given packet flow for processing. A processing function is applied to each of the packet flows within the processing engines and the processed packets are output on a time-shared, arbitered data bus coupled to the plurality of processing engines.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Aug 20 00:00:00 EDT 2013},
month = {Tue Aug 20 00:00:00 EDT 2013}
}
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Works referenced in this record:
Access control method for multiprocessor systems
patent, February 1986
- Hatada, Minoru; Ishida, Hideaki; Matsushita, Masatoshi
- US Patent Document 4,571,672
Method and apparatus for data decompression in the presence of memory hierarchies
patent, April 2010
- Biran, Giora; Franke, Hubertus; Golander, Amit
- US Patent Document 7,692,561
Authentication engine architecture and method
patent, February 2007
- Buer, Mark; Law, Patrick; Qi, Zheng
- US Patent Document 7,177,421
Packet processing in a multiple processor system
patent, June 2010
- Zuk, Nir; Mao, Yu Ming
- US Patent Document 7,746,862
System resource arbitration mechanism for a host bridge
patent, April 2001
- Hayek, George R.; Langendorf, Brian K.; Kundu, Aniruddha
- US Patent Document 6,212,589