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Title: Virtually addressed caches for multiprogramming and multiprocessing environments

Thesis/Dissertation ·
OSTI ID:5968441

A technique was devised to allow the use of virtually addressed cache by multiple processes sharing global memory without cache coherency problems. When the question of how to best combine I/O subsystems with virtually addressed cache using that technique was raised, several more problems were discovered. These included the MMU coherency problem and the question of whether the MMU should be associated with the processor or with main memory. The advantages and disadvantages of a large number of locations of processors, caches, buses, MMUs, and main memories were discussed. Associating the MMU(s) with main memory rather than with the cache or the processor has a number of advantages. These advantages include a solution to the MMU coherency problem, better performance, virtual addresses for I/O which yields uniform addresses for all references, and simplicity of design. An implementation of the ideas developed in this dissertation is proposed. The system to be implemented is a multiprocessor workstation using shared global memory for multiprocessing and multiprogramming tasks. Operating system and system software issues are discussed.

Research Organization:
Washington Univ., Seattle (USA)
OSTI ID:
5968441
Resource Relation:
Other Information: Thesis (Ph. D.)
Country of Publication:
United States
Language:
English

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