A VLSI chip set for a multiprocessor workstation; Part II: A memory management unit and cache controller
Journal Article
·
· IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA)
- Dept. of Electrical and Computer Sciences, Univ. of California, Berkeley, CA (US)
This paper describes a memory management unit and a cache controller (MMU/CC) for a shared memory multiprocessor. The MMU/CC implements a novel memory management scheme, called in-cache address translation, that does not require a translation lookaside buffer (TLB). It also implements a snooping but protocol to maintain data consistency across all caches in the system. Both chips are implemented in a 1.6-{mu}m double-layer-metal CMOS technology, and are being used in a multiprocessor workstation (SPUR) successfully executing a UNIX-like network-based operating system called Sprite as well as many applications including LISP programs.
- OSTI ID:
- 6845349
- Journal Information:
- IEEE Journal of Solid-State Circuits (Institute of Electrical and Electronics Engineers); (USA), Vol. 24:6; ISSN 0018-9200
- Country of Publication:
- United States
- Language:
- English
Similar Records
The SPUR instruction unit: An on-chip instruction cache memory for a high performance VLSI multiprocessor
Verifying a multiprocessor cache controller using random case generation
Bus and cache memory organizations for multiprocessors
Book
·
Thu Jan 01 00:00:00 EST 1987
·
OSTI ID:6845349
Verifying a multiprocessor cache controller using random case generation
Book
·
Sun Jan 01 00:00:00 EST 1989
·
OSTI ID:6845349
Bus and cache memory organizations for multiprocessors
Miscellaneous
·
Sun Jan 01 00:00:00 EST 1989
·
OSTI ID:6845349