Quasi-cyclic binary burst error-correcting codes, MEC-SBC codes and VLSI self-checking decoders
The reliability of VLSI digital systems can be enhanced by the use of error-control codes and self-checking decoders. Rate-1/2 and rate-2/3 majority logic decodable quasi-cyclic binary burst error-correcting codes are constructed. A new class of quasi-cyclic binary-burst error-correcting codes is studied based upon product codes. The true maximum-burst error-correcting capability for each code in the class is given. In certain cases the codes reduce to Gilbert codes. Often codes exist in the class that have the same block length and number of check bits as the Gilbert codes but correct longer bursts of errors than Gilbert codes. By shortening the codes, one can design codes such that the burst error-correcting capability of the codes are increased. Sometimes the shortened codes achieve the Reiger bound. A critrion for designing MEC-SBC codes is presented. Procedures for designing DEC-SBC (3, 1)/sub m/ codes using the ordinary basis and the normal basis are proposed. A method for designing DEC-SBC (4, 2)/sub m/ codes is given. Some good codes found by computer search are introduced. Three dual-rail VLSI circuits are developed for designing self-checking decoders. Two self-checking decoders and a redundant syndrome former are constructed.
- Research Organization:
- Massachusetts Univ., Amherst (USA)
- OSTI ID:
- 5371080
- Resource Relation:
- Other Information: Thesis (Ph. D.)
- Country of Publication:
- United States
- Language:
- English
Similar Records
Entanglement-assisted quantum low-density parity-check codes
Totally self-checking checker for a parallel unordered coding scheme