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Title: SEU mitigation for half-latches in xilinx virtex FPGAs.

Abstract

The performance, in-system reprogrammability, flexibility, and reduced costs of SRAM-based field-programmable gate arrays (FPGAs) make them very interesting for high-speed, on-orbit data processing, but, because the current generation of radiation-tolerant SRAM-based FPGAs are derived directly from COTS versions of the chips, their memory structures are still susceptible to single-event upsets (SEUs) . While previous papers have described the SEU characteristics and mitigation techniques for the configuration and user memory structures on the Xilinx Virtex family of FPGAs, we will concentrate on the effects of SEUs on 'half-latch' structures within the Virtex architecture, describe techniques for mitigating these effects, and provide new experimental data which illustrate the effectiveness of one of these mitigation techniques under proton radiation.

Authors:
 [1];  [2];  [3];  [4];  [5]
  1. Paul S.
  2. Michael Paul
  3. Michael J.
  4. Darrel Eric
  5. Nathan
Publication Date:
Research Org.:
Los Alamos National Laboratory (LANL), Los Alamos, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
976550
Report Number(s):
LA-UR-03-0859
Journal ID: ISSN 0018--9499; TRN: US1006478
Resource Type:
Conference
Resource Relation:
Journal Volume: 50; Journal Issue: 6; Conference: Submitted to: IEEE Nuclear and Space Radiation Effects Conference, July 21-25, 2003, Monterey, CA, USA
Country of Publication:
United States
Language:
English
Subject:
72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS; COMPUTER ARCHITECTURE; CONFIGURATION; DATA PROCESSING; FLEXIBILITY; MITIGATION; PERFORMANCE; PROTONS; RADIATION EFFECTS; COMPUTERS; SPACE FLIGHT

Citation Formats

Graham, P S, Caffrey, M P, Wirthlin, M J, Johnson, D E, and Rollins, N. SEU mitigation for half-latches in xilinx virtex FPGAs.. United States: N. p., 2003. Web. doi:10.1109/TNS.2003.820744.
Graham, P S, Caffrey, M P, Wirthlin, M J, Johnson, D E, & Rollins, N. SEU mitigation for half-latches in xilinx virtex FPGAs.. United States. https://doi.org/10.1109/TNS.2003.820744
Graham, P S, Caffrey, M P, Wirthlin, M J, Johnson, D E, and Rollins, N. 2003. "SEU mitigation for half-latches in xilinx virtex FPGAs.". United States. https://doi.org/10.1109/TNS.2003.820744. https://www.osti.gov/servlets/purl/976550.
@article{osti_976550,
title = {SEU mitigation for half-latches in xilinx virtex FPGAs.},
author = {Graham, P S and Caffrey, M P and Wirthlin, M J and Johnson, D E and Rollins, N},
abstractNote = {The performance, in-system reprogrammability, flexibility, and reduced costs of SRAM-based field-programmable gate arrays (FPGAs) make them very interesting for high-speed, on-orbit data processing, but, because the current generation of radiation-tolerant SRAM-based FPGAs are derived directly from COTS versions of the chips, their memory structures are still susceptible to single-event upsets (SEUs) . While previous papers have described the SEU characteristics and mitigation techniques for the configuration and user memory structures on the Xilinx Virtex family of FPGAs, we will concentrate on the effects of SEUs on 'half-latch' structures within the Virtex architecture, describe techniques for mitigating these effects, and provide new experimental data which illustrate the effectiveness of one of these mitigation techniques under proton radiation.},
doi = {10.1109/TNS.2003.820744},
url = {https://www.osti.gov/biblio/976550}, journal = {},
issn = {0018--9499},
number = 6,
volume = 50,
place = {United States},
year = {Wed Jan 01 00:00:00 EST 2003},
month = {Wed Jan 01 00:00:00 EST 2003}
}

Conference:
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