Method and apparatus for communicating computer data from one point to another over a communications medium
- Chippewa Falls, WI
- Sumner, WA
- Eau Claire, WI
- Altoona, WI
The present invention is directed toward a communications channel comprising a link level protocol, a driver, a receiver, and a canceller/equalizer. The link level protocol provides logic for DC-free signal encoding and recovery as well as supporting many features including CRC error detection and message resend to accommodate infrequent bit errors across the medium. The canceller/equalizer provides equalization for destabilized data signals and also provides simultaneous bi-directional data transfer. The receiver provides bit deskewing by removing synchronization error, or skewing, between data signals. The driver provides impedance controlling by monitoring the characteristics of the communications medium, like voltage or temperature, and providing a matching output impedance in the signal driver so that fewer distortions occur while the data travels across the communications medium.
- Research Organization:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- W-7405-ENG-48
- Assignee:
- Silicon Graphics, Inc. (Sunnyvale, CA)
- Patent Number(s):
- 7,248,635
- Application Number:
- 09/620,373
- OSTI ID:
- 913096
- Country of Publication:
- United States
- Language:
- English
Performance of the RamLink memory architecture
|
conference | January 1994 |
110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock
|
journal | January 1999 |
RamLink: a high-bandwidth point-to-point memory architecture
|
conference | January 1992 |
Time-domain response of multiconductor transmission lines
|
journal | June 1987 |
A 900 Mb/s bidirectional signaling scheme
|
journal | January 1995 |
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