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Title: Apparatus and method for defect testing of integrated circuits

Patent ·
OSTI ID:872882
 [1]
  1. Placitas, NM
+ Show Author Affiliations

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Research Organization:
Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)
DOE Contract Number:
AC04-94AL85000
Assignee:
Sandia Corporation (Albuquerque, NM)
Patent Number(s):
US 6031386
OSTI ID:
872882
Country of Publication:
United States
Language:
English

References (8)

On the effect of I/sub SSQ/ testing in reducing early failure rate conference January 1995
IC failure analysis: techniques and tools for quality reliability improvement journal May 1993
I/sub DD/ pulse response testing on analog and digital CMOS circuits conference January 1993
High resolution I/sub DDQ/ characterization and testing-practical issues conference January 1996
Digital integrated circuit testing using transient signal analysis conference January 1996
A general purpose I/sub DDQ/ measurement circuit conference January 1993
I DDQ testing: A review journal December 1992
Iddq test: sensitivity analysis of scaling conference January 1996

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