Process for 3D chip stacking

Patent · Thu Jan 01 00:00:00 EST 1998

OSTI ID:871964

Malba, Vincent ^[1]

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1. Livermore, CA

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• DOE Contract Number: W-7405-ENG-48
• Assignee: Regents of University of California (Oakland, CA)
• Patent Number(s): US 5834162
• OSTI ID: 871964
• Country of Publication: United States
• Language: English

Related Subjects

process
3d
chip
stacking
manufacturable
fabricating
electrical
interconnects
extend
top
surface
integrated
circuit
sidewall
laser
pantography
pattern
dimensional
l-connect
l-shaped
type
implements
moving
conventional
bond
interface
pads
implementation
holding
individual
chips
batch
processing
depositing
dielectric
passivation
layer
sidewalls
vias
forming
removing
means
enables
cost
manufacturing
increased
performance
reduced
space
functional
unit
volume
passivation layer
top surface
integrated circuit
process enables
unit volume
batch processing
batch process
bond pads
circuit chip
laser pantography
electrical interconnects
interface pads
electrical interconnect
laser pantograph
manufacturable process
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