Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

Warren, William L; Vanheusden, Karel J. R.; Schwank, James R; Fleetwood, Daniel M; Shaneyfelt, Marty R; Winokur, Peter S; Devine, Roderick A. B.

Title: Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

Patent · Tue Jul 28 00:00:00 EDT 1998

OSTI ID:871740

Warren, William L ^[1]; Vanheusden, Karel J. R. ^[1]; Schwank, James R ^[1]; Fleetwood, Daniel M ^[1]; Shaneyfelt, Marty R ^[1]; Winokur, Peter S ^[1]; Devine, Roderick A. B. ^[2]

Albuquerque, NM
St. Martin le Vinoux, FR

A method for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus-voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer.

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Research Organization:: Sandia National Laboratories (SNL), Albuquerque, NM, and Livermore, CA (United States)

DOE Contract Number:: AC04-94AL85000

Assignee:: Sandia Corporation (Albuquerque, NM)

Patent Number(s):: US 5786231

OSTI ID:: 871740

Country of Publication:: United States

Language:: English

References (9)

Oxygen gettering and oxide degradation during annealing of Si/SiO ₂ /Si structures Devine, R. A. B.; Warren, W. L.; Xu, J. B. Journal of Applied Physics, Vol. 77, Issue 1 https://doi.org/10.1063/1.359365	journal	January 1995
Molecular hydrogen, E' center hole traps, and radiation induced interface traps in MOS devices Conley, J. F.; Lenahan, P. M. IEEE Transactions on Nuclear Science, Vol. 40, Issue 6 https://doi.org/10.1109/23.273534	journal	January 1993
Combined electron spin resonance and capacitance‐voltage analysis of hydrogen‐annealing induced positive charge in buried SiO ₂ Vanheusden, K.; Stesmans, A.; Afanas’ev, V. V. Journal of Applied Physics, Vol. 77, Issue 6 https://doi.org/10.1063/1.359571	journal	March 1995
Low dose SIMOX for ULSI applications Auberton-Hervé, A. J.; Aspar, B.; Pelloie, J. L. Physical and Technical Problems of SOI Structures and Devices https://doi.org/10.1007/978-94-011-0109-7_1	book	January 1995
Positive charging of buried SiO ₂ by hydrogenation Vanheusden, K.; Stesmans, A. Applied Physics Letters, Vol. 64, Issue 19 https://doi.org/10.1063/1.111530	journal	May 1994
SOI Materials Colinge, Jean-Pierre Silicon-on-Insulator Technology https://doi.org/10.1007/978-1-4757-2121-8_2	book	January 1991
Excess‐Si related defect centers in buried SiO ₂ thin films Warren, W. L.; Fleetwood, D. M.; Shaneyfelt, M. R. Applied Physics Letters, Vol. 62, Issue 25 https://doi.org/10.1063/1.109061	journal	June 1993
Characterization and depth profiling of E ’ defects in buried SiO ₂ Vanheusden, K.; Stesmans, A. Journal of Applied Physics, Vol. 74, Issue 1 https://doi.org/10.1063/1.354103	journal	July 1993
Ultraviolet radiation induced defect creation in buried SiO ₂ layers Devine, R. A. B.; Leray, J‐L.; Margail, J. Applied Physics Letters, Vol. 59, Issue 18 https://doi.org/10.1063/1.106042	journal	October 1991

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screening
method
selecting
semiconductor
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defects
below
predetermined
level
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layer
qualifying
integrated
circuit
fabrication
comprises
steps
annealing
substrate
temperature
defect-activating
ambient
hydrogen
forming
gas
ammonia
sufficient
time
activating
measuring
defect-revealing
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capacitance-versus-voltage
c-v
current-versus-voltage
i-v
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silicon-on-insulator
separation
implantation
oxygen
simox
process
bond
etch
besoi
silicon
thermal
deposited
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forming gas
electrical charge
silicon substrates
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semiconductor substrate
method comprises
silicon substrate
integrated circuit
oxide layer
sufficient time
predetermined level
formed thereon
semiconductor substrates
substrates formed
method comprise
insulator substrate
defects therein
electrical characteristic
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Title: Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

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References (9)

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