High speed imager test station

Patent · Sun Jan 01 00:00:00 EST 1995

OSTI ID:870158

Yates, George J ^[1]; Albright, Kevin L ^[2]; Turko, Bojan T ^[3]

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1. Santa Fe, NM
2. Los Alamos, NM
3. Moraga, CA

A test station enables the performance of a solid state imager (herein called a focal plane array or FPA) to be determined at high image frame rates. A programmable waveform generator is adapted to generate clock pulses at determinable rates for clock light-induced charges from a FPA. The FPA is mounted on an imager header board for placing the imager in operable proximity to level shifters for receiving the clock pulses and outputting pulses effective to clock charge from the pixels forming the FPA. Each of the clock level shifters is driven by leading and trailing edge portions of the clock pulses to reduce power dissipation in the FPA. Analog circuits receive output charge pulses clocked from the FPA pixels. The analog circuits condition the charge pulses to cancel noise in the pulses and to determine and hold a peak value of the charge for digitizing. A high speed digitizer receives the peak signal value and outputs a digital representation of each one of the charge pulses. A video system then displays an image associated with the digital representation of the output charge pulses clocked from the FPA. In one embodiment, the FPA image is formatted to a standard video format for display on conventional video equipment.

• Research Organization: Los Alamos National Laboratory (LANL), Los Alamos, NM (United States)
• DOE Contract Number: W-7405-ENG-36
• Assignee: Regents of University of California, Office of Technology (Alameda, CA)
• Patent Number(s): US 5467128
• OSTI ID: 870158
• Country of Publication: United States
• Language: English

Related Subjects

speed
imager
station
enables
performance
solid
called
focal
plane
array
fpa
determined
image
frame
rates
programmable
waveform
generator
adapted
generate
clock
pulses
determinable
light-induced
charges
mounted
header
board
placing
operable
proximity
level
shifters
receiving
outputting
effective
charge
pixels
forming
driven
leading
trailing
edge
portions
reduce
power
dissipation
analog
circuits
receive
output
clocked
condition
cancel
noise
determine
hold
peak
value
digitizing
digitizer
receives
signal
outputs
digital
representation
video
displays
associated
embodiment
formatted
standard
format
display
conventional
equipment
plane array
charge pulses
edge portions
power dissipation
clock pulse
trailing edge
focal plane
waveform generator
clock pulses
edge portion
peak value
output charge
standard video
reduce power
analog circuit
digital representation
signal value
video format
speed digitizer
programmable waveform
/348/702/