A proposal for a UPC memory consistency model, v1.0
The memory consistency model in a language defines the order in which the results of write operations maybe observed through read operations. The behavior of a UPC program may depend on the timing of accesses to shared variables, so a program defines a set of possible executions, rather than a single execution. The memory consistency model constrains the set of possible executions for a given program; the user may then rely on properties that are true of all of those executions. The memory consistency model is defined in terms of the read and write operations issued by each thread in naive translation of the code, i.e., without any code transformations by the compiler, with each thread issuing operations as defined by the abstract machine defined in ISO C 5.1.2.3. A UPC compiler or run time system may perform various code transformations to improve performance, so long as they are not visible to the programmer - i.e., provided the set of externally-visible behaviors (the input/output dynamics and volatile behavior defined in ISO C 5.1.2.3) from any execution of the transformed program are identical to those of the original program executing on the abstract machine and adhering to the consistency model defined in this document.
- Research Organization:
- Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
- Sponsoring Organization:
- USDOE Director. Office of Science. Computational and Environmental Research; Hewlett-Packard Company (US)
- DOE Contract Number:
- AC03-76SF00098
- OSTI ID:
- 823757
- Report Number(s):
- LBNL-54983; R&D Project: K52004; TRN: US200415%%566
- Resource Relation:
- Other Information: PBD: 5 May 2004
- Country of Publication:
- United States
- Language:
- English
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