Hash sorter - firmware implementation and an application for the Fermilab BTeV level 1 trigger system

Wu, Jinyuan

Title: Hash sorter - firmware implementation and an application for the Fermilab BTeV level 1 trigger system

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Abstract

A hardware hash sorter for the Fermilab BTeV Level 1 trigger system will be presented. The has sorter examines track-segment data before the data are sent to a system comprised of 2500 Level 1 processors, and rearranges the data into bins based on the slope of track segments. They have found that by using the rearranged data, processing time is significantly reduced allowing the total number of processors required for the Level 1 trigger system to be reduced. The hash sorter can be implemented in an FPGA that is already included as part of the design of the trigger system. Hash sorting has potential applications in a broad area in trigger and DAQ systems. It is a simple O(n) process and is suitable for FPGA implementation. Several implementation strategies will also be discussed in this document.

Authors:: Wu, Jinyuan

Publication Date:: Wed Nov 05 00:00:00 EST 2003

Research Org.:: Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)

Sponsoring Org.:: USDOE Office of Energy Research (ER) (US)

OSTI Identifier:: 816968

Report Number(s):: FERMILAB-Conf-03/357-E
TRN: US0305159

DOE Contract Number:: AC02-76CH03000

Resource Type:: Conference

Resource Relation:: Conference: IEEE NSS 2003, Portland, OR (US), 10/19/2003--10/25/2003; Other Information: PBD: 5 Nov 2003

Country of Publication:: United States

Language:: English

Subject:: 43 PARTICLE ACCELERATORS; DESIGN; FERMILAB; IMPLEMENTATION; PROCESSING; SORTING

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                    Wu, Jinyuan. Hash sorter - firmware implementation and an application for the Fermilab BTeV level 1 trigger system.  United States: N. p., 2003. 
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                    Wu, Jinyuan. Hash sorter - firmware implementation and an application for the Fermilab BTeV level 1 trigger system.  United States.

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                    Wu, Jinyuan. 2003.  
        "Hash sorter - firmware implementation and an application for the Fermilab BTeV level 1 trigger system".  United States.  https://www.osti.gov/servlets/purl/816968.

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@article{osti_816968,

  title        = {Hash sorter - firmware implementation and an application for the Fermilab BTeV level 1 trigger system},

  author       = {Wu, Jinyuan},

  abstractNote = {A hardware hash sorter for the Fermilab BTeV Level 1 trigger system will be presented. The has sorter examines track-segment data before the data are sent to a system comprised of 2500 Level 1 processors, and rearranges the data into bins based on the slope of track segments. They have found that by using the rearranged data, processing time is significantly reduced allowing the total number of processors required for the Level 1 trigger system to be reduced. The hash sorter can be implemented in an FPGA that is already included as part of the design of the trigger system. Hash sorting has potential applications in a broad area in trigger and DAQ systems. It is a simple O(n) process and is suitable for FPGA implementation. Several implementation strategies will also be discussed in this document.},

  doi          = {},

  url          = {https://www.osti.gov/biblio/816968},
  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Wed Nov 05 00:00:00 EST 2003},

  month        = {Wed Nov 05 00:00:00 EST 2003}

}

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