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Title: Intelligent trigger processor for the crystal box

Conference ·
OSTI ID:6569552

A large solid angle modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor changing decays of muon. A beam of up to 10/sup 6/ muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor described in this paper. Further reduction to < 1 Hz is achieved by a microprocessor based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic loci. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex the data acquisition channels and apply additional event filtering.

Research Organization:
Los Alamos National Laboratory (LANL), Los Alamos, NM (United States); Stanford Univ., CA (United States)
DOE Contract Number:
W-7405-ENG-36
OSTI ID:
6569552
Report Number(s):
LA-UR-81-1323; CONF-810539-1; TRN: 81-009481
Resource Relation:
Conference: Conference on the application of microprocessors to high energy physics experiments, Geneva, Switzerland, 4 May 1981
Country of Publication:
United States
Language:
English