Bermuda Triangle: a subsystem of the 168/E interfacing scheme used by Group B at SLAC
The Bermuda Triangle system is a method of interfacing several 168/E microprocessors to a central system for control of the processors and overlaying their memories. The system is a three-way interface with I/O ports to a large buffer memory, a PDP11 Unibus and a bus to the 168/E processors. Data may be transferred bidirectionally between any two ports. Two Bermuda Triangles are used, one for the program memory and one for the data memory. The program buffer memory stores the overlay programs for the 168/E, and the data buffer memory, the incoming raw data, the data portion of the overlays, and the outgoing processed events. This buffering is necessary since the memories of 168/E microprocessors are small compared to the main program and the amount of data being processed. The link to the computer facility is via a Unibus to IBM channel interface. A PDP11/04 controls the data flow. 7 figures, 4 tables. (RWR)
- Research Organization:
- SLAC National Accelerator Lab., Menlo Park, CA (United States)
- DOE Contract Number:
- EY-76-C-03-0515
- OSTI ID:
- 5786766
- Report Number(s):
- SLAC-TN-79-7; TRN: 80-002950
- Country of Publication:
- United States
- Language:
- English
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