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Title: Development of a time-to-digital converter ASIC for the upgrade of the ATLAS Monitored Drift Tube detector

Journal Article · · Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment
 [1];  [2];  [1];  [3];  [1];  [1];  [1];  [1];  [3]
  1. Univ. of Michigan, Ann Arbor, MI (United States)
  2. University of Science and Technology of China, Anhui (China); Univ. of Michigan, Ann Arbor, MI (United States)
  3. University of Science and Technology of China, Anhui (China)
+ Show Author Affiliations

The upgrade of the ATLAS muon spectrometer for the high-luminosity LHC requires new trigger and readout electronics for various elements of the detector. We present the design of a time-to-digital converter (TDC) ASIC prototype for the ATLAS Monitored Drift Tube (MDT) detector. The chip was fabricated in a GlobalFoundries 130 nm CMOS technology. Lastly, studies indicate that its timing and power dissipation characteristics meet the design specifications, with a timing bin variation of 40 ps for all 48 TDC slices and a power dissipation of about 6.5 mW per slice.

Research Organization:
Univ. of Michigan, Ann Arbor, MI (United States)
Sponsoring Organization:
USDOE Office of Science (SC), High Energy Physics (HEP)
Grant/Contract Number:
SC0007859; SC0008062; AC02-98CH10886
OSTI ID:
1638969
Alternate ID(s):
OSTI ID: 1549040
Journal Information:
Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment, Vol. 880, Issue C; ISSN 0168-9002
Publisher:
ElsevierCopyright Statement
Country of Publication:
United States
Language:
English
Citation Metrics:
Cited by: 9 works
Citation information provided by
Web of Science

References (5)

ATLAS Muon Drift Tube Electronics journal September 2008
FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades journal December 2015
A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS journal December 2012
Full-speed testing of A/D converters journal December 1984
Interpolating time counter with 100 ps resolution on a single FPGA device journal January 2000

Figures / Tables (13)

Fig. 1(p. 2)figure Fig. 1
Fig. 2(p. 3)figure Fig. 2
Fig. 3(p. 3)figure Fig. 3
Table 1(p. 4)table Table 1
Fig. 4(p. 5)figure Fig. 4
Fig. 5(p. 5)figure Fig. 5
Fig. 6(p. 6)figure Fig. 6
Fig. 7(p. 6)figure Fig. 7
Fig. 8(p. 7)figure Fig. 8
Fig. 9(p. 7)figure Fig. 9
Fig. 10(p. 8)figure Fig. 10
Fig. 11(p. 8)figure Fig. 11
Fig. 12(p. 8)figure Fig. 12

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Related Subjects

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
TDC
ASIC
ATLAS
MDT