skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Smart memory buffers

Patent ·
OSTI ID:1637874
; ; ;

An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

Research Organization:
Hewlett Packard Enterprise Development LP, Houston, TX (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
SC0005026
Assignee:
Hewlett Packard Enterprise Development LP (Houston, TX)
Patent Number(s):
10,585,602
Application Number:
16/011,187
OSTI ID:
1637874
Resource Relation:
Patent File Date: 06/18/2018
Country of Publication:
United States
Language:
English

References (24)

Memory Management System and Method patent-application October 2008
Method for performing a RAID stripe write operation using a drive XOR command set patent April 1998
Systems, Methods, and Apparatuses for Hybrid Memory patent-application June 2011
Synchronization method for loosely coupled arrays of redundant disk drives patent January 1996
Storage Subsystem patent-application September 2011
XOR controller for a storage subsystem patent January 1997
i-NVMM conference June 2011
Securely and Autonomously Synchronizing Data in a Distributed Computing Environment patent-application July 2002
Hybrid Volatile and Non-Volatile Memory Device patent-application May 2010
Read-Modify-Write Protocol for Maintaining Parity Coherency in a Write-Back Distributed Redundancy Data Storage System patent-application August 2011
Data pipelining method and apparatus for memory control circuit patent April 2002
Redundant Array of Independent Storage patent-application August 2011
Data storage device matrix architecture patent August 1996
PDRAM: a hybrid PRAM and DRAM main memory system conference January 2009
Scalable high performance main memory system using phase-change memory technology
  • Qureshi, Moinuddin K.; Srinivasan, Vijayalakshmi; Rivers, Jude A.
  • Proceedings of the 36th annual international symposium on Computer architecture - ISCA '09 https://doi.org/10.1145/1555754.1555760
conference January 2009
Memory System and Method of Using Same patent-application February 2003
Data File Migration from a Mirrored Raid to a Non-Mirrored XOR-Based Raid without Rewriting the Data patent-application October 2003
Method of Managing a Solid State Drive, Associated Systems and Implementations patent-application April 2010
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems conference June 2011
Memory controller using time-staggered lockstep sub-channels with buffered memory patent November 2011
Methods and arrangements for hybrid data storage patent September 2009
Page placement in hybrid memory systems conference January 2011
Method and system for detecting fraudulent data update patent November 1999
Hybrid memory device with single interface patent May 2010

Similar Records

Related Subjects

97 MATHEMATICS AND COMPUTING