Semiconductor power device including wire or ribbon bonds over device active region
A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.
- Research Organization:
- Integra Technologies, Inc., El Segundo, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- SC0017898
- Assignee:
- Integra Technologies, Inc. (El Segundo, CA)
- Patent Number(s):
- 10,593,610
- Application Number:
- 16/027,074
- OSTI ID:
- 1637842
- Resource Relation:
- Patent File Date: 07/03/2018
- Country of Publication:
- United States
- Language:
- English
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