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Title: Bit error protection in cache memories

Patent ·
OSTI ID:1568719
; ;

A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344; B609201
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
10,379,944
Application Number:
15/489,438
OSTI ID:
1568719
Resource Relation:
Patent File Date: 04/17/2017
Country of Publication:
United States
Language:
English

References (13)

Error detection schemes for a unified cache in a data processing system patent March 2012
Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines patent October 2008
Method and apparatus for using cache memory in a system that supports a low power state patent January 2014
Handling of hard errors in a cache of a data processing apparatus patent March 2015
System, method and computer executable program for information tracking from heterogeneous sources patent August 2011
System and method for distributing trusted time patent August 2008
Parallel instruction processing and operand integrity verification patent June 2010
Error detection schemes for a cache in a data processing system patent October 2012
System and methods for distributing trusted time patent October 2014
Error correction using iterating generation of data syndrome patent October 2009
Soft error detection in a memory system patent November 2017
Technique for partitioning data to correct memory part failures patent November 2002
Programmable error actions for a cache in a data processing system patent January 2012

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Related Subjects

97 MATHEMATICS AND COMPUTING