Collective memory transfer devices and methods for multiple-core processors
This disclosure provides systems, methods, and apparatus for collective memory transfers. A control unit may be configured to coordinate a transfer of data between a memory and processor cores. For a read data transfer operation, the control unit may receive a trigger packet identifying a read data transfer operation and identifying a first plurality of data lines based on data values included in the trigger packet. The control unit may read the first plurality of data lines from the memory sequentially and send a second plurality of data lines to the processor cores. For a write data transfer operation, the control unit may send a request for at least one data line to a plurality of processor cores, may receive and reorder the requested data lines, and may write the data lines to a memory. The control unit may determine a mapping between processor cores and the memory.
- Research Organization:
- Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC02-05CH11231
- Assignee:
- The Regents of the University of California (Oakland, CA)
- Patent Number(s):
- 10,318,444
- Application Number:
- 14/250,085
- OSTI ID:
- 1568459
- Resource Relation:
- Patent File Date: 04/10/2014
- Country of Publication:
- United States
- Language:
- English
System, Apparatus, and Method for Modifying the Order of Memory Accesses
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patent-application | April 2011 |
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