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Title: Error detection and correction utilizing locally stored parity information

Patent ·
OSTI ID:1568154
;

A processing system includes a memory coupled to a processor. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344; B600716
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
10,248,497
Application Number:
14/521,183
OSTI ID:
1568154
Resource Relation:
Patent File Date: 10/22/2014
Country of Publication:
United States
Language:
English

References (11)

Error detection and correction code for data and check code fields patent March 2000
Methods and apparatus for correcting data and error detection codes on the fly patent March 2007
Circuit for and method of implementing a plurality of circuits on a programmable logic device patent August 2008
Dynamic Management of Heterogenous Memory patent-application August 2014
Memory-based error recovery patent January 2013
Protection of data in memory patent February 2016
Shared cache for data integrity operations patent February 2004
Method and apparatus for recovering from correctable ECC errors patent June 1999
System and method of reading non-volatile computer memory patent August 2008
Error correcting device, method of error correction thereof, and memory device and data processing system including of the same patent November 2012
Method of correcting errors stored in a memory array patent May 2009

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