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Title: Optimizing TLB entries for mixed page size storage in contiguous memory

Patent ·
OSTI ID:1532129
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A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.

Research Organization:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B554331
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
8,856,490
Application Number:
13/618,730
OSTI ID:
1532129
Resource Relation:
Patent File Date: 2012-09-14
Country of Publication:
United States
Language:
English

References (8)

System and Method for Cache-Locking Mechanism Using Translation Table Attributes for Replacement Class ID Determination patent-application January 2009
Multi-Petascale Highly Efficient Parallel Supercomputer patent-application September 2011
TLB parity error recovery patent May 2005
Block address translation circuit using two-bit to four-bit encoder patent May 1999
Mapping an arbitrary number of contiguous memory pages at an arbitrary alignment patent February 2007
Translation look-aside buffer with variable page sizes patent April 2012
Method and Apparatus for Efficient Replacement Algorithm for Pre-Fetcher Oriented Data Cache patent-application December 2008
Optimized scalable network switch patent December 2007

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