System and method for hardware scheduling of conditional barriers and impatient barriers
A method and a system are provided for hardware scheduling of barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated, and when each thread reaches the barrier instruction during execution of program, it is determined whether the thread participates in the barrier instruction. The threads that participate in the barrier instruction are then serially executed to process one or more instructions of the program that follow the barrier instruction. A method and system are also provided for impatient scheduling of barrier instructions. When a portion of the threads that is greater than a minimum number of threads and less than all of the threads in the plurality of threads reaches the barrier instruction each of the threads in the portion is serially executed to process one or more instructions of the program that follow the barrier instruction.
- Research Organization:
- NVIDIA Corp. Santa Clara, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- B599861
- Assignee:
- NVIDIA Corporation (Santa Clara, CA)
- Patent Number(s):
- 9,448,803
- Application Number:
- 13/794,578
- OSTI ID:
- 1531944
- Resource Relation:
- Patent File Date: 2013-03-11
- Country of Publication:
- United States
- Language:
- English
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