Dynamic remapping of cache lines
Patent
·
OSTI ID:1531936
A method of managing cache memory includes accessing a cache memory at a primary index that corresponds to an address specified in an access request. A determination is made that accessing the cache memory at the primary index does not result in a cache hit on a cache line with an error-free status. In response to this determination, the primary index is mapped to a secondary index and data for the address is written to a cache line at the secondary index.
- Research Organization:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC52-07NA27344; B600716
- Assignee:
- Advanced Micro Devices, Inc. (Sunnyvale, CA)
- Patent Number(s):
- 9,424,195
- Application Number:
- 14/253,785
- OSTI ID:
- 1531936
- Resource Relation:
- Patent File Date: 2014-04-15
- Country of Publication:
- United States
- Language:
- English
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