Analyzing the suitability of contemporary 3D-stacked PIM architectures for HPC scientific applications

Conference · Mon Apr 01 00:00:00 EDT 2019

DOI:https://doi.org/10.1145/3310273.3322831· OSTI ID:1530065

Peng, Ivy Bo ^[1]; Vetter, Jeffrey S.  ^[1]; Moore, Shirley V.  ^[1]; Joydeep, Rakshit ^[2]; Markidis, Stefano ^[3]

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1. ORNL
2. Intel Labs
3. KTH Royal Institute of Technology, Stockholm, Sweden

Scaling off-chip bandwidth is challenging due to fundamental limitations, such as a fixed pin count and plateauing signaling rates. Recently, vendors have turned to 2.5D and 3D stacking to closely integrate system components. Interestingly, these technologies can integrate a logic layer under multiple memory dies, enabling computing capability inside a memory stack. This trend in stacking is making PIM architectures commercially viable. In this work, we investigate the suitability of offloading kernels in scientific applications onto 3D stacked PIM architectures. We evaluate several hardware constraints resulted from the stacked structure. We perform extensive simulation experiments and in-depth analysis to quantify the impact of application locality in TLBs, data caches, and memory stacks. Our results also identify design optimization areas in software and hardware for HPC scientific applications.

• Research Organization: Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
• Sponsoring Organization: USDOE Office of Science (SC)
• DOE Contract Number: AC05-00OR22725
• OSTI ID: 1530065
• Resource Relation: Conference: International Conference on Computing Frontiers - Alghero, , Italy - 4/30/2019 4:00:00 AM-5/2/2019 4:00:00 AM
• Country of Publication: United States
• Language: English