ATLAS FTK Challenge: Simulation of a Billion-fold Hardware Parallelism

Conference · Thu Jan 01 00:00:00 EST 2015

DOI:https://doi.org/10.1016/j.procs.2015.11.061· OSTI ID:1528960

Adelman, J; Ancu, L S; Annovi, A; Baines, J; Britzger, D; Ehrenfeld, W; Giannetti, P; Luongo, C; Pandini, C; Schmitt, S; Vaniachine, A

During the current LHC shutdown period the ATLAS experiment will upgrade the Trigger and Data Acquisition system to include a hardware tracker coprocessor: the Fast TracKer (FTK). The FTK receives data from the 80 million of channels of the ATLAS silicon detector, identifying charged tracks and reconstructing their parameters at a rate of up to 100 KHz and within 100 microseconds. To achieve this performance, the FTK system identifies candidate tracks utilizing the computing power of a custom ASIC chip with associative memory (AM) designed to perform “pattern matching” at very high speed; track parameters are then calculated using modern FPGAs. A detailed simulation of this massive system has been developed with the goal of supporting the hardware design and studying its impact in the ATLAS online event selection at high LHC luminosities. We present the issues related to emulating FTK on a general-purpose CPU platform, using ATLAS computing Grid resources, and the solutions developed in order to mitigate these problems and allow the studies required to support the system design, construction and installation.

• Research Organization: Argonne National Lab. (ANL), Argonne, IL (United States)
• Sponsoring Organization: USDOE Office of Science - Office of High Energy Physics
• DOE Contract Number: AC02-06CH11357
• OSTI ID: 1528960
• Resource Relation: Conference: 16th International workshop on Advanced Computing and Analysis Techniques in physics research, 09/01/14 - 09/05/14, Prague, CZ
• Country of Publication: United States
• Language: English

Related Subjects

Distributed Computing
Simulation