EXPERIENCE WITH FPGA-BASED PROCESSOR CORE AS FRONT-END COMPUTER.
The RHIC control system architecture follows the familiar ''standard model''. LINUX workstations are used as operator consoles. Front-end computers are distributed around the accelerator, close to equipment being controlled or monitored. These computers are generally based on VMEbus CPU modules running the VxWorks operating system. I/O is typically performed via the VMEbus, or via PMC daughter cards (via an internal PCI bus), or via on-board I/O interfaces (Ethernet or serial). Advances in FPGA size and sophistication now permit running virtual processor ''cores'' within the FPGA logic, including ''cores'' with advanced features such as memory management. Such systems offer certain advantages over traditional VMEbus Front-end computers. Advantages include tighter coupling with FPGA logic, and therefore higher I/O bandwidth, and flexibility in packaging, possibly resulting in a lower noise environment and/or lower cost. This paper presents the experience acquired while porting the RHIC control system to a PowerPC 405 core within a Xilinx FPGA for use in low-level RF control.
- Research Organization:
- Brookhaven National Lab. (BNL), Upton, NY (United States)
- Sponsoring Organization:
- DOE/SC
- DOE Contract Number:
- DE-AC02-98CH10886
- OSTI ID:
- 15020386
- Report Number(s):
- BNL-74979-2005-CP; R&D Project: 18072; KB-02-02-01-1; TRN: US0504324
- Resource Relation:
- Conference: 10TH INTERNATIONAL CONFERENCE ON ACCELERATOR AND LARGE EXPERIMENTAL PHYSICS CONTROL SYSTEMS (ICALECPS) 2005; GENEVA, SWITZERLAND; 20051010 through 20051014
- Country of Publication:
- United States
- Language:
- English
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