Development of a low-inductance SiC trench MOSFET power module for high-frequency application

Conference · Thu Mar 01 00:00:00 EST 2018

DOI:https://doi.org/10.1109/APEC.2018.8341419· OSTI ID:1474666

Wang, Zhiqiang  ^[1]; Yang, Fei ^[2]; Campbell, Steven  ^[1]; Chinthavali, Madhu Sudhan  ^[1]

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1. ORNL
2. University of Tennessee, Knoxville (UTK)

This paper deals with the development of a low-inductance multiple-chip power module with state-of-art 1200 V SiC Trench MOSFETs for high-frequency application. Specifically, a phase-leg power module package with integrated decoupling capacitance is fabricated based on P-cell/N-cell concept, and the packaging design is discussed in detail. Dedicated double pulse test is built, and a gate driver with cross-talk suppression function is designed to support the fast switching speed operation of SiC Trench MOSFETs. The parasitic inductance and current density distribution of the power module are simulated and extracted for the purpose of voltage spike limiting. The temperature dependent static and switching characteristics of the developed module are evaluated as well, and the key differences from traditional SiC double-diffused MOS (DMOS) are identified and discussed. Based on the turn-off switching characterization results, a lumped equivalent power-loop parasitic inductance of ~6 nH is achieved for the designed power module.

• Research Organization: Oak Ridge National Laboratory (ORNL), Oak Ridge, TN (United States)
• Sponsoring Organization: USDOE Office of Energy Efficiency and Renewable Energy (EERE)
• DOE Contract Number: AC05-00OR22725
• OSTI ID: 1474666
• Resource Relation: Conference: 2018 IEEE Applied Power Electronics Conference and Exposition (APEC) - San Antonio, Texas, United States of America - 3/4/2018 5:00:00 AM-3/8/2018 5:00:00 AM
• Country of Publication: United States
• Language: English