System architecture and hardware design of the CDF XFT online track processor

Conference · Fri Nov 05 00:00:00 EST 1999

DOI:https://doi.org/10.1109/NSSMIC.1999.842491· OSTI ID:14365

Holm, Scott

A trigger track processor is being designed for CDF Run 2. This processor identifies high momentum (P{sub T} > 1.5 GeV/c) charged tracks in the new central outer tracking chamber for the CDF II detector. The design of the track processor, called the eXtremely Fast Tracker (XFT), is highly parallel and handle an input rate of 183 Gbits/sec and output rate of 44 Gbits/sec. The XFT is pipelined and reports the results for a new event every 132ns. The XFT uses three stages, hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in Programmable Logic Devices (PLDs) which allow for in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. Prototypes of each of these modules have been designed and built, and are working. An overview of the hardware design and the system architecture are presented.

• Research Organization: Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
• Sponsoring Organization: USDOE Office of Energy Research (ER) (US)
• DOE Contract Number: AC02-76CH03000
• OSTI ID: 14365
• Report Number(s): FERMILAB-Conf-99/317; TRN: US0111018
• Resource Relation: Journal Volume: 1; Conference: 1999 IEEE Nuclear Science Symposium and Medical Imaging Conference, Seattle, WA (US), 10/24/1999--10/30/1999; Other Information: PBD: 5 Nov 1999
• Country of Publication: United States
• Language: English

Related Subjects

43 PARTICLE ACCELERATORS
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY
ALGORITHMS
CLASSIFICATION
DESIGN
FERMILAB COLLIDER DETECTOR
MODIFICATIONS
PATTERN RECOGNITION
DIELECTRIC TRACK DETECTORS
PARTICLE TRACKS
DATA ACQUISITION SYSTEMS