Readout Chip for an L1 Tracking Trigger Using Asynchronous Logic
- UCLA
Adding a silicon based tracker to the level 1 trigger systems for LHC detectors can substantially increase the ability of these systems to find events with patterns of high Pt tracks. This is especially true for high luminosity running where there may be several hundred interactions per crossing. Cooling and mass constraints require that the readout chips have low power and generate little electrical noise. The LHC crossing clock and experiment trigger latency requires that a trigger be able to be made in less than 100 LHC crossings of 25 ns each. One way to minimize power and noise is to use asynchronous logic. We present a readout chip design for both level 1 trigger and event readout that is entirely asynchronous. The only clock used is the LHC crossing clock.
- Research Organization:
- Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC), High Energy Physics (HEP)
- Contributing Organization:
- CMS
- DOE Contract Number:
- AC02-07CH11359
- OSTI ID:
- 1419284
- Report Number(s):
- FERMILAB-CONF-12-411-PPD; 1124253
- Journal Information:
- JINST, Vol. 7; Conference: 2nd Workshop on Intelligent Trackers, Pisa, Italy, 05/03-05/05/2012
- Country of Publication:
- United States
- Language:
- English
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