Topology-Aware Performance Optimization and Modeling of Adaptive Mesh Refinement Codes for Exascale
- Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
- Sandia National Lab. (SNL-CA), Livermore, CA (United States)
Here, we introduce a topology-aware performance optimization and modeling workflow for AMR simulation that includes two new modeling tools, ProgrAMR and Mota Mapper, which interface with the BoxLib AMR framework and the SSTmacro network simulator. ProgrAMR allows us to generate and model the execution of task dependency graphs from high-level specifications of AMR-based applications, which we demonstrate by analyzing two example AMR-based multigrid solvers with varying degrees of asynchrony. Mota Mapper generates multiobjective, network topology-aware box mappings, which we apply to optimize the data layout for the example multigrid solvers. While the sensitivity of these solvers to layout and execution strategy appears to be modest for balanced scenarios, the impact of better mapping algorithms can be significant when performance is highly constrained by network hop latency. Furthermore, we show that network latency in the multigrid bottom solve is the main contributing factor preventing good scaling on exascale-class machines.
- Research Organization:
- Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC), Advanced Scientific Computing Research (ASCR)
- Grant/Contract Number:
- AC02-05CH11231
- OSTI ID:
- 1379689
- Journal Information:
- 2016 First International Workshop on Communication Optimizations in HPC (COMHPC), Conference: 2016 First Workshop on Optimization of Communication in HPC (COMHPC), Salt Lake City, UT (United States), 18 Nov 2016
- Country of Publication:
- United States
- Language:
- English
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