Low-Voltage Complementary Electronics from Ion-Gel-Gated Vertical Van der Waals Heterostructures

Choi, Yongsuk; Kang, Junmo; Jariwala, Deep; Kang, Moon Sung; Marks, Tobin J.; Hersam, Mark C.; Cho, Jeong Ho

doi:10.1002/adma.201506450

Title: Low-Voltage Complementary Electronics from Ion-Gel-Gated Vertical Van der Waals Heterostructures

Journal Article · Tue Mar 22 00:00:00 EDT 2016 · Advanced Materials

DOI:https://doi.org/10.1002/adma.201506450· OSTI ID:1371245

Choi, Yongsuk ^[1]; Kang, Junmo ^[2]; Jariwala, Deep ^[2]; Kang, Moon Sung ^[3]; Marks, Tobin J. ^[2]; Hersam, Mark C. ^[2]; Cho, Jeong Ho ^[1]

Sungkyunkwan Univ., Suwon (Republic of Korea); Northwestern Univ., Evanston, IL (United States)
Northwestern Univ., Evanston, IL (United States)
Soongsil Univ., Seoul (Korea)

Graphene has attracted significant attention for high performance electronics due to its superior electronic and physical properties. Yet, the absence of a band gap and the resulting poor semiconducting properties of graphene have prevented its use as the active layer for transistors in digital logic applications. In contrast, alternative two-dimensional (2D) materials based on transition metal dichalcogenides (TMDCs) exhibit desirable semiconducting properties that have re-energized the development of 2D digital logic circuits. Specifically, graphene-TMDC heterojunctions have been explored as gate-tunable Schottky barrier devices due to the readily tunable work function of graphene that is enabled by its linear energy dispersion. In these devices, the electrical current is modulated by tuning the injection barrier height at the graphene-TMDC heterojunction through an applied gate potential, resulting in vertical field-effect transistors (VFETs) with high on/off current ratios suitable for digital electronics.[26-32] However, existing VFET designs have employed oxide gate dielectric layers with large operating voltage windows not suitable for modern-day electronics. Moreover, complementary VFETs with low threshold voltages have not been demonstrated, which implies that the necessary conditions for low-power integrated circuits have not yet been achieved in this device geometry.

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Research Organization:: Northwestern Univ., Evanston, IL (United States). Energy Frontier Research Center (EFRC) Argonne-Northwestern Solar Energy Research Center (ANSER)

Sponsoring Organization:: USDOE Office of Science (SC), Basic Energy Sciences (BES); National Science Foundation (NSF)

Grant/Contract Number:: SC0001059

OSTI ID:: 1371245

Journal Information:: Advanced Materials, Vol. 28, Issue 19; Related Information: ANSER partners with Northwestern University (lead); Argonne National Laboratory; University of Chicago; University of Illinois, Urbana-Champaign; Yale University; ISSN 0935-9648

Publisher:: WileyCopyright Statement

Country of Publication:: United States

Language:: English

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Cited by: 74 works

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