Many-core applications to online track reconstruction in HEP experiments
- Padua U.
- Los Alamos
- Fermilab
- INFN, Rome
- Cornell U.
Interest in parallel architectures applied to real time selections is growing in High Energy Physics (HEP) experiments. In this paper we describe performance measurements of Graphic Processing Units (GPUs) and Intel Many Integrated Core architecture (MIC) when applied to a typical HEP online task: the selection of events based on the trajectories of charged particles. We use as benchmark a scaled-up version of the algorithm used at CDF experiment at Tevatron for online track reconstruction – the SVT algorithm – as a realistic test-case for low-latency trigger systems using new computing architectures for LHC experiment. We examine the complexity/performance trade-off in porting existing serial algorithms to many-core devices. Measurements of both data processing and data transfer latency are shown, considering different I/O strategies to/from the parallel devices.
- Research Organization:
- Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC), High Energy Physics (HEP)
- DOE Contract Number:
- AC02-07CH11359
- OSTI ID:
- 1331808
- Report Number(s):
- FERMILAB-CONF-14-501-CD; arXiv:1311.0380; 1263254
- Journal Information:
- J.Phys.Conf.Ser., Vol. 513; Conference: 20th International Conference on Computing in High Energy and Nuclear Physics, Amsterdam, The Netherlands, 10/14-10/18/2013
- Country of Publication:
- United States
- Language:
- English
Similar Records
Developement of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)
Performance study of GPUs in real-time trigger applications for HEP experiments