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Title: Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

Abstract

A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

Inventors:
; ; ; ;
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1226234
Patent Number(s):
9,190,392
Application Number:
14/283,101
Assignee:
Sandia Corporation
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Patent
Resource Relation:
Patent File Date: 2014 May 20
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE; 42 ENGINEERING

Citation Formats

Shinde, Subhash L., Teifel, John, Flores, Richard S., Jarecki Jr., Robert L., and Bauer, Todd. Three-dimensional stacked structured ASIC devices and methods of fabrication thereof. United States: N. p., 2015. Web.
Shinde, Subhash L., Teifel, John, Flores, Richard S., Jarecki Jr., Robert L., & Bauer, Todd. Three-dimensional stacked structured ASIC devices and methods of fabrication thereof. United States.
Shinde, Subhash L., Teifel, John, Flores, Richard S., Jarecki Jr., Robert L., and Bauer, Todd. 2015. "Three-dimensional stacked structured ASIC devices and methods of fabrication thereof". United States. https://www.osti.gov/servlets/purl/1226234.
@article{osti_1226234,
title = {Three-dimensional stacked structured ASIC devices and methods of fabrication thereof},
author = {Shinde, Subhash L. and Teifel, John and Flores, Richard S. and Jarecki Jr., Robert L. and Bauer, Todd},
abstractNote = {A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.},
doi = {},
url = {https://www.osti.gov/biblio/1226234}, journal = {},
number = ,
volume = ,
place = {United States},
year = {Thu Nov 19 00:00:00 EST 2015},
month = {Thu Nov 19 00:00:00 EST 2015}
}

Works referenced in this record:

Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs
journal, December 2010


3D-MAPS: 3D Massively parallel processor with stacked memory
conference, February 2012

  • Kim, Dae Hyun; Athikulwongse, Krit; Healy, Michael
  • 2012 IEEE International Solid- State Circuits Conference - (ISSCC), 2012 IEEE International Solid-State Circuits Conference
  • https://doi.org/10.1109/ISSCC.2012.6176969

Yield and Cost Modeling for 3D Chip Stack Technologies
conference, September 2006


A CMOS-3D reconfigurable architecture with in-pixel processing for feature detectors
conference, January 2012


Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study
conference, January 2009


Cost effectiveness of 3D integration options
conference, November 2010


Structured ASIC, evolution or revolution?
conference, January 2004


A customized design of DRAM controller for on-chip 3D DRAM stacking
conference, September 2010