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Title: Area-efficient physically unclonable function circuit architecture

Abstract

Generating a physically a physically unclonable function ("PUF") circuit value includes comparing each of first identification components in a first bank to each of second identification components in a second bank. A given first identification component in the first bank is not compared to another first identification component in the first bank and a given second identification component in the second bank is not compared to another second identification component in the second bank. A digital bit value is generated for each comparison made while comparing each of the first identification components to each of the second identification components. A PUF circuit value is generated from the digital bit values from each comparison made.

Inventors:
; ; ; ;
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1178669
Patent Number(s):
9,018,972
Application Number:
13/906,628
Assignee:
Sandia Corporation (Albuquerque, NM)
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013 May 31
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Gurrieri, Thomas, Hamlet, Jason, Bauer, Todd, Helinski, Ryan, and Pierson, Lyndon G. Area-efficient physically unclonable function circuit architecture. United States: N. p., 2015. Web.
Gurrieri, Thomas, Hamlet, Jason, Bauer, Todd, Helinski, Ryan, & Pierson, Lyndon G. Area-efficient physically unclonable function circuit architecture. United States.
Gurrieri, Thomas, Hamlet, Jason, Bauer, Todd, Helinski, Ryan, and Pierson, Lyndon G. 2015. "Area-efficient physically unclonable function circuit architecture". United States. https://www.osti.gov/servlets/purl/1178669.
@article{osti_1178669,
title = {Area-efficient physically unclonable function circuit architecture},
author = {Gurrieri, Thomas and Hamlet, Jason and Bauer, Todd and Helinski, Ryan and Pierson, Lyndon G},
abstractNote = {Generating a physically a physically unclonable function ("PUF") circuit value includes comparing each of first identification components in a first bank to each of second identification components in a second bank. A given first identification component in the first bank is not compared to another first identification component in the first bank and a given second identification component in the second bank is not compared to another second identification component in the second bank. A digital bit value is generated for each comparison made while comparing each of the first identification components to each of the second identification components. A PUF circuit value is generated from the digital bit values from each comparison made.},
doi = {},
url = {https://www.osti.gov/biblio/1178669}, journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Apr 28 00:00:00 EDT 2015},
month = {Tue Apr 28 00:00:00 EDT 2015}
}

Works referenced in this record:

A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations
journal, January 2008


A technique to build a secret key in integrated circuits for identification and authentication applications
conference, January 2004


Energy Scalable Universal Hashing
journal, December 2005


Extended abstract: The butterfly PUF protecting IP on every FPGA
conference, June 2008


Fuzzy Extractors: How to Generate Strong Keys from Biometrics and Other Noisy Data
journal, January 2008


LFSR-based Hashing and Authentication
conference, January 1994


Physical unclonable functions for device authentication and secret key generation
conference, January 2007


Physical Unclonable Functions and Public-Key Crypto for FPGA IP Protection
conference, August 2007


Silicon physical random functions
conference, January 2002


A physical unclonable function defined using power distribution system equivalent resistance variations
conference, January 2009


IC identification circuit using device mismatch
conference, January 2000


Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system
conference, January 2010


Comb Capacitor Structures for On-Chip Physical Uncloneable Function
journal, February 2009


LISA: Maximizing RO PUF's secret extraction
conference, June 2010

  • Yin, Chi-En; Qu, Gang
  • 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2010), 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)
  • https://doi.org/10.1109/HST.2010.5513105

Self-timed thermally-aware circuits and methods of use thereof
patent, August 2008


Securely field configurable device
patent, April 2010


Volatile device keys and applications thereof
patent, November 2010


Authentication of integrated circuits
patent, November 2010


Method and system for authentication of a physical object
patent, October 2011


Authentication with physical unclonable functions
patent, July 2014


Method for protecting information carrier comprising an integrated circuit
patent-application, February 2007


Controlling Access to Device-Specific Information
patent-application, August 2007


Sharing a secret by using random function
patent-application, March 2008


Authentication with Physical Unclonable Functions
patent-application, March 2009


Physically Unclonable Function Implemented Through Threshold Voltage Comparison
patent-application, December 2011


Works referencing / citing this record: