Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems
Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of applied gate voltage field induced carriers in essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, and containing a single metallurgical doping type, and functional combinations thereof. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents utilizing material(s) which form rectifying junctions with both N and P-type semiconductor whether metallurigically or field induced.
- Research Organization:
- ~Individually Owned Patent
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- FG47-93R701314
- Assignee:
- Welch, James D.
- Patent Number(s):
- 6,624,493
- Application Number:
- 09/716,046
- OSTI ID:
- 1174501
- Country of Publication:
- United States
- Language:
- English
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