Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition
A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.
- Research Organization:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- B554331
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 8,447,960
- Application Number:
- 12/684,860
- OSTI ID:
- 1083955
- Country of Publication:
- United States
- Language:
- English
System, method, and computer program product for conditionally suspending issuing instructions of a thread
|
patent | March 2010 |
Executing multiple threads in a processor
|
patent | December 2010 |
Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor
|
patent | November 2009 |
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