High-speed, multi-channel detector readout electronics for fast radiation detectors
In this project, we are developing a high speed digital spectrometer that a) captures detector waveforms at rates up to 500 MSPS b) has upgraded event data acquisition with additional data buffers for zero dead time operation c) moves energy calculations to the FPGA to increase spectrometer throughput in fast scintillator applications d) uses a streamlined architecture and high speed data interface for even faster readout to the host PC These features are in addition to the standard functions in our existing spectrometers such as digitization, programmable trigger and energy filters, pileup inspection, data acquisition with energy and time stamps, MCA histograms, and run statistics. In Phase I, we upgraded one of our existing spectrometer designs to demonstrate the key principle of fast waveform capture using a 500 MSPS, 12 bit ADC and a Xilinx Virtex-4 FPGA. This upgraded spectrometer, named P500, performed well in initial tests of energy resolution, pulse shape analysis, and timing measurements, thus achieving item (a) above. In Phase II, we are revising the P500 to build a commercial prototype with the improvements listed in items (b)-(d). As described in the previous report, two devices were built to pursue this goal, named the Pixie-500 and the Pixie-500 Express. The Pixie-500 has only minor improvements from the Phase I prototype and is intended as an early commercial product (its production and part of its development were funded outside the SBIR). It also allows testing of the ADC performance in real applications.The Pixie-500 Express (or Pixie-500e) includes all of the improvements (b)-(d). At the end of Phase II of the project, we have tested and debugged the hardware, firmware and software of the Pixie-500 Express prototype boards delivered 12/3/2010. This proved substantially more complex than anticipated. At the time of writing, all hardware bugs have been fixed, the PCI Express interface is working, the SDRAM has been successfully tested and the SHARC DSP has been booted with preliminary code. All new ICs and circuitry on the prototype are working properly, however some of the planned firmware and software functions have not yet been completely implemented and debugged. Overall, due to the unanticipated complexity of the PCI Express interface, some aspects of the project could not be completed with the time and funds available in Phase II. These aspects will be completed in self-funded Phase III.
- Research Organization:
- XIA LLC, Hayward, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- FG02-08ER84981
- OSTI ID:
- 1043826
- Report Number(s):
- DOE-FG02-08ER84981; TRN: US1400011
- Country of Publication:
- United States
- Language:
- English
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