A bipolar analog front-end integrated circuit for the SDC silicon tracker
A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker. The IC was designed and tested at LBL and was fabricated using AT&T`s CBIC-U2, 4 GHz f{sub T} complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 {mu}m pitch double-sided silicon strip detector. The chip measures 6.8 mm {times} 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a {Phi}=10{sup 14} protons/cm{sup 2} have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process.
- Research Organization:
- Lawrence Berkeley Lab., CA (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- AC03-76SF00098
- OSTI ID:
- 10114598
- Report Number(s):
- LBL-34864; CONF-931107-32; ON: DE94005203; TRN: 94:002251
- Resource Relation:
- Conference: 1993 IEEE nuclear science symposium and medical imaging conference,San Francisco, CA (United States),2-5 Nov 1993; Other Information: PBD: Nov 1993
- Country of Publication:
- United States
- Language:
- English
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