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  1. Mode selection and tuning of single-frequency short-cavity VECSELs

    Here, we report on mode selection and tuning properties of vertical-external-cavity surface-emitting lasers (VECSELs) containing coupled semiconductor and external cavities of total length less than 1 mm. Our goal is to create narrowlinewidth (<1MHz) single-frequency VECSELs that operate near 850 nm on a single longitudinal cavity resonance and tune versus temperature without mode hops. We have designed, fabricated, and measured VECSELs with external-cavity lengths ranging from 25 to 800 μm. Lastly, we compare simulated and measured coupled-cavity mode frequencies and discuss criteria for single mode selection.
  2. VCSELs for Interferometric Readout of MEMS Sensors.

    Abstract not provided.
  3. VCSELs for Interferometric Readout of MEMS Sensors.

    Abstract not provided.
  4. Heterogeneous Integration of III-V Photonics and Silicon Electronics for Advanced Optical Microsystems.

    Abstract not provided.
  5. Heterogeneous Integration of III-V Photonics and Silicon Electronics for Advanced Optical Microsystems.

    Abstract not provided.
  6. Thermal Design and Characterization of Heterogeneously Integrated InGaP/GaAs HBTs.

    Abstract not provided.
  7. Plasmonic Modulators Using Quantum Well Electroabsorption.

    Abstract not provided.
  8. Low-Power VCSEL-Based Optical Interconnects.

    Abstract not provided.
  9. 850-nm VCSELs optimized for cryogenic data transmission.

    Abstract not provided.
  10. Thermal Design and Characterization of Heterogeneously Integrated InGaP/GaAs HBTs

    Flip-chip heterogeneously integrated n-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with integrated thermal management on wide-bandgap AlN substrates followed by GaAs substrate removal are demonstrated. Without thermal management, substrate removal after integration significantly aggravates self-heating effects, causing poor I–V characteristics due to excessive device self-heating. An electrothermal codesign scheme is demonstrated that involves simulation (design), thermal characterization, fabrication, and evaluation. Thermoreflectance thermal imaging, electrical-temperature sensitive parameter-based thermometry, and infrared thermography were utilized to assess the junction temperature rise in HBTs under diverse configurations. In order to reduce the thermal resistance of integrated devices, passive cooling schemes assisted by structural modification, i.e.,more » positioning indium bump heat sinks between the devices and the carrier, were employed. By implementing thermal heat sinks in close proximity to the active region of flip-chip integrated HBTs, the junction-to-baseplate thermal resistance was reduced over a factor of two, as revealed by junction temperature measurements and improvement of electrical performance. In conclusion, the suggested heterogeneous integration method accounts for not only electrical but also thermal requirements providing insight into realization of advanced and robust III–V/Si heterogeneously integrated electronics.« less
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"Geib, Kent M."

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