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Title: Implementing inverted master-slave 3D semiconductor stack

Patent ·
OSTI ID:1241310
; ;

A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.

Research Organization:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B601996
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
9,281,302
Application Number:
14/184,868
OSTI ID:
1241310
Resource Relation:
Patent File Date: 2014 Feb 20
Country of Publication:
United States
Language:
English

References (12)

Semiconductor chip carrier package with a heat sink patent December 1986
Stacked silicon die carrier assembly patent July 1995
High density integrated circuit module patent July 2005
Method and system for stacking integrated circuits patent April 2010
Semiconductor device and method of stacking same size semiconductor die electrically connected through conductive via formed around periphery of the die patent November 2011
Implementing multiple different types of dies for memory stacking patent January 2013
Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device patent August 2013
Mountable Integrated Circuit Package System with Intra-Stack Encapsulation patent-application July 2009
Packaged Semiconductor Device for High Performance Memory and Logic patent-application July 2012
Stacked Semiconductor Devices Including a Master Device patent-application April 2013
Semiconductor Die Assemblies with Enhanced Thermal Management, Semiconductor Devices Including Same and Related Methods patent-application May 2013
Power Distribution for 3D Semiconductor Package patent-application April 2015

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