Module partitioning and interlaced data placement schemes to reduce conflicts in interleaved memories
Abstract
In interleaved memories, interference between concurrently active vector streams results in memory bank conflicts and reduced bandwidth. In this paper, we present two schemes for reducing inter-vector interference. First, we propose a memory module partitioning technique in which disjoint access sets are created for each of the concurrent vectors. Various properties of the involved address mapping are presented. Then we present an interlaced data placement scheme, where the simultaneously accessed vectors are interlaced and stored to the memory. Performance of the two schemes are evaluated by trace driven simulation. It is observed that the schemes have significant merit in reducing the interference in interleaved memories and increasingly the effective memory bandwidth. The schemes are applicable to memory systems for superscalar processors, vector supercomputers and parallel processors.
- Authors:
-
- Univ. of South Florida, Tampa, FL (United States)
- Pennsylvania State Univ., University Park, PA (United States)
- Publication Date:
- OSTI Identifier:
- 98906
- Report Number(s):
- CONF-940856-
TRN: 94:008346-0038
- Resource Type:
- Conference
- Resource Relation:
- Conference: 1994 international conference on parallel processing, St. Charles, IL (United States), 15-19 Aug 1994; Other Information: PBD: 1994; Related Information: Is Part Of Proceedings of the 1994 international conference on parallel processing. Volume 1: Architecture; Agrawal, D.P. [ed.]; PB: 330 p.
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 99 MATHEMATICS, COMPUTERS, INFORMATION SCIENCE, MANAGEMENT, LAW, MISCELLANEOUS; COMPUTER NETWORKS; DESIGN; MEMORY MANAGEMENT; DATA TRANSMISSION; EFFICIENCY; PARALLEL PROCESSING; COMPUTER ARCHITECTURE
Citation Formats
Kurian, L, Choi, B, Hulina, P T, and Coraor, L D. Module partitioning and interlaced data placement schemes to reduce conflicts in interleaved memories. United States: N. p., 1994.
Web.
Kurian, L, Choi, B, Hulina, P T, & Coraor, L D. Module partitioning and interlaced data placement schemes to reduce conflicts in interleaved memories. United States.
Kurian, L, Choi, B, Hulina, P T, and Coraor, L D. 1994.
"Module partitioning and interlaced data placement schemes to reduce conflicts in interleaved memories". United States.
@article{osti_98906,
title = {Module partitioning and interlaced data placement schemes to reduce conflicts in interleaved memories},
author = {Kurian, L and Choi, B and Hulina, P T and Coraor, L D},
abstractNote = {In interleaved memories, interference between concurrently active vector streams results in memory bank conflicts and reduced bandwidth. In this paper, we present two schemes for reducing inter-vector interference. First, we propose a memory module partitioning technique in which disjoint access sets are created for each of the concurrent vectors. Various properties of the involved address mapping are presented. Then we present an interlaced data placement scheme, where the simultaneously accessed vectors are interlaced and stored to the memory. Performance of the two schemes are evaluated by trace driven simulation. It is observed that the schemes have significant merit in reducing the interference in interleaved memories and increasingly the effective memory bandwidth. The schemes are applicable to memory systems for superscalar processors, vector supercomputers and parallel processors.},
doi = {},
url = {https://www.osti.gov/biblio/98906},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Sat Dec 31 00:00:00 EST 1994},
month = {Sat Dec 31 00:00:00 EST 1994}
}