Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer

Byun, Jong-Ho; Ravindran, Arun; Mukherjee, Arindam; Joshi, Bharat; Chassin, David P

doi:10.1109/FCCM.2009.23

Title: Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer

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Abstract

The computationally intensive power flow problem determines the voltage magnitude and phase angle at each bus in a power system for hundreds of thousands of buses under balanced three-phase steady-state conditions. We report an FPGA acceleration of the Gauss-Seidel based power flow solver employed in the transmission module of the GridLAB-D power distribution simulator and analysis tool. The prototype hardware is implemented on an SGI Altix-RASC system equipped with a Xilinx Virtex II 6000 FPGA. Due to capacity limitations of the FPGA, only the bus voltage calculations of the power network are implemented on hardware while the branch current calculations are implemented in software. For a 200,000 bus system, the bus voltage calculation on the FPGA achieves a 48x speed-up with PQ buses and a 62 times for PV over an equivalent sequential software implementation. The average overall speed up of the FPGA-CPU implementation with 100 iterations of the Gauss-Seidel power solver is 2.6x over a software implementation, with the branch calculations on the CPU accounting for 85% of the total execution time. The FPGA-CPU implementation also shows linear scaling with increase in the size of the input power network.

Authors:: Byun, Jong-Ho; Ravindran, Arun; Mukherjee, Arindam; Joshi, Bharat; Chassin, David P

Publication Date:: Tue Sep 01 00:00:00 EDT 2009

Research Org.:: Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 972557

Report Number(s):: PNNL-SA-64099
TD5016010; TRN: US201006%%136

DOE Contract Number:: AC05-76RL01830

Resource Type:: Conference

Resource Relation:: Conference: 17th IEEE Symposium on Field Programmable Custom Computing Machines, April 5-7, 2009, Napa, California, 227-230

Country of Publication:: United States

Language:: English

Subject:: 24 POWER TRANSMISSION AND DISTRIBUTION; ACCELERATION; BUSES; CAPACITY; COMPUTERS; IMPLEMENTATION; PERFORMANCE; POWER DISTRIBUTION; POWER SYSTEMS; SIMULATORS; STEADY-STATE CONDITIONS; VELOCITY

Citation Formats


                    Byun, Jong-Ho, Ravindran, Arun, Mukherjee, Arindam, Joshi, Bharat, and Chassin, David P. Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer.  United States: N. p., 2009. 
        Web.  doi:10.1109/FCCM.2009.23.

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                    Byun, Jong-Ho, Ravindran, Arun, Mukherjee, Arindam, Joshi, Bharat, & Chassin, David P. Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer.  United States.  https://doi.org/10.1109/FCCM.2009.23

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                    Byun, Jong-Ho, Ravindran, Arun, Mukherjee, Arindam, Joshi, Bharat, and Chassin, David P. 2009.  
        "Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer".  United States.  https://doi.org/10.1109/FCCM.2009.23.

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@article{osti_972557,

  title        = {Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer},

  author       = {Byun, Jong-Ho and Ravindran, Arun and Mukherjee, Arindam and Joshi, Bharat and Chassin, David P},

  abstractNote = {The computationally intensive power flow problem determines the voltage magnitude and phase angle at each bus in a power system for hundreds of thousands of buses under balanced three-phase steady-state conditions. We report an FPGA acceleration of the Gauss-Seidel based power flow solver employed in the transmission module of the GridLAB-D power distribution simulator and analysis tool. The prototype hardware is implemented on an SGI Altix-RASC system equipped with a Xilinx Virtex II 6000 FPGA. Due to capacity limitations of the FPGA, only the bus voltage calculations of the power network are implemented on hardware while the branch current calculations are implemented in software. For a 200,000 bus system, the bus voltage calculation on the FPGA achieves a 48x speed-up with PQ buses and a 62 times for PV over an equivalent sequential software implementation. The average overall speed up of the FPGA-CPU implementation with 100 iterations of the Gauss-Seidel power solver is 2.6x over a software implementation, with the branch calculations on the CPU accounting for 85% of the total execution time. The FPGA-CPU implementation also shows linear scaling with increase in the size of the input power network.},

  doi          = {10.1109/FCCM.2009.23},

  url          = {https://www.osti.gov/biblio/972557},
  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {Tue Sep 01 00:00:00 EDT 2009},

  month        = {Tue Sep 01 00:00:00 EDT 2009}

}

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