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Title: Scalable Parallel Utopia

This contribution proposes a 128 bit wide interface structure clocked at approximately 80 MHz that will operate at 10 Gbps as a strawman for a 0C192C Utopia Specification. In addition, the concept of scalable width of data transfers in order to maintain manageably low clock rates is proposed.
Authors:
;
Publication Date:
OSTI Identifier:
756
Report Number(s):
SAND98-2228C
ON: DE00000756
DOE Contract Number:
AC04-94AL85000
Resource Type:
Conference
Resource Relation:
Conference: The ATM Forum Technical Committee; Gold Coast, Australia; 10/5-9/1998
Research Org:
Sandia National Laboratories, Albuquerque, NM, and Livermore, CA
Sponsoring Org:
USDOE
Country of Publication:
United States
Language:
English
Subject:
99 MATHEMATICS, COMPUTERS, INFORMATION SCIENCE, MANAGEMENT, LAW, MISCELLANEOUS; Sandia National Laboratories; Computers; Equipment Interfaces