Transistor sizing in the design of high-speed CMOS (complementary-symmetry metal-oxide-semiconductor) super buffers. Master's thesis

Technical Report · Tue Mar 01 00:00:00 EST 1988

OSTI ID:7059031

Steele, G R

An algorithm for sizing transistors for static Complementary-symmetry Metal-Oxide-Semiconductor (CMOS) integrated-circuit logic design using silicon-gate enhancement-mode Field-Effect Transistors (FET) is derived and implemented in software. The algorithm is applied to the mask-level hardware design of a three-micron-minimum feature-size p-well high-speed super buffer. A software representation of the super buffer can be used for the automated design of custom Very-Large-Scale Integrated (VLSI) circuits.

• Research Organization: Naval Postgraduate School, Monterey, CA (USA)
• OSTI ID: 7059031
• Report Number(s): AD-A-196526/8/XAB
• Resource Relation: Other Information: Thesis
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
COMPUTER-AIDED DESIGN
ALGORITHMS
FIELD EFFECT TRANSISTORS
INTEGRATED CIRCUITS
LOGIC CIRCUITS
BUFFERS
ELECTRONIC CIRCUITS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
SEMICONDUCTOR DEVICES
TRANSISTORS
420800* - Engineering- Electronic Circuits & Devices- (-1989)
990220 - Computers
Computerized Models
& Computer Programs- (1987-1989)