Architectures and design techniques for real-time image processing ICs
A set of 8 chips, which perform real-time image processing tasks, was designed and fabricated with a 4..mu.. MNOS technology. The chips include: a 3 x 3 linear convolver, a 3 x 3 sorting filter, a 7 x 7 logical convolver, a contour tracer, a feature extractor, a look-up table ROM, and two post processors for the linear convolver. All chips were designed using architectures dedicated to the particular image processing tasks to be performed. The image processing circuits operate on 10-MHz video data (512 x 512 pixel images). The design time for the chips was kept to 1.5 man years by re-using hardware and, in addition, utilizing and developing some appropriate CAD tools. ROM generators and a data-path generator were developed to reduce the circuit design time. An image-recognition system was built with these custom chips that can recognize two dimensional objects that are characterized by their closed outer contours. The complete system is controlled by a SUN work station and operates at rates up to 15 frame/Sec. The recognition system achieved a 97% recognition rate for 8 objects over a wide range of orientation and size variations and a 100% recognition rate without size variations.
- Research Organization:
- California Univ., Berkeley (USA)
- OSTI ID:
- 6842445
- Resource Relation:
- Other Information: Thesis (Ph. D.)
- Country of Publication:
- United States
- Language:
- English
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