On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement

Journal Article · Sat Apr 01 00:00:00 EST 1989 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/12.21144· OSTI ID:5818533

Kim, J H; Reddy, S M

The continuing growth of interest in systolic arrays poses the problem of ensuring an acceptable yield. In this paper, the authors propose a unified approach to the design of fault-tolerant systolic arrays incorporating design for testability, a testing scheme, a reconfiguration algorithm, time complexity analysis of the proposed reconfiguration algorithm, and yield analysis. A main feature of the proposed designs is that multiple PE's in a 2-D array can be tested simultaneously, thus reducing the testing time significantly. Another feature is that with introduction of delay registers, the proposed reconfiguration algorithm reconfigures a faulty 2-D systolic array into a fault-free array without reducing throughput. The overall aim of this paper is to provide a design for a 2-D systolic array that produces high yield in VLSI/WSI implementations.

• Research Organization: 9508863; 3348000
• OSTI ID: 5818533
• Journal Information: IEEE Trans. Comput.; (United States), Vol. 38:4
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
ALGORITHMS
FAULT TOLERANT COMPUTERS
DESIGN
INTEGRATED CIRCUITS
PERFORMANCE TESTING
TWO-DIMENSIONAL CALCULATIONS
COMPUTERS
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
TESTING
990210* - Supercomputers- (1987-1989)