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Title: ESD evaluation of radiation-hardened, high-reliability CMOS and MNOS ICs

Conference ·
OSTI ID:5750911

Standard human-body-equivalent circuit electrostatic discharge (ESD) tests were performed on the inputs of high-reliability, radiation-hardened integrated circuits (ICs) designed with seven different technologies. Metal and silicon gate complementary MOS (CMOS) and metal-nitride-oxide-semiconductor (MNOS) ICs with design rules ranging from 10 microns down to 2 microns were evaluated. The ESD hardness of these ICs ranged from 1 kV to greater than 9 kV. The low-range ESD hardness ICs were fabricated with a masking polysilicon ring that defined the input protection diodes. Tests on commercial equivalent ICs demonstrated that the ESD hardness of the radiation-hardened ICs was not significantly less than the ESD hardness of the commercial equivalent ICs. The failure modes and mechanisms of the ICs were evaluated. Most of the ICs that did not have the masking polysilicon ring failed because of input to V/sub DD/ or V/sub SS/ shorts due to degraded protection diodes. ESD tests with the pulse applied between the package metal lid and the package pins were also performed. These lid tests produced permanent input damage, the same as occurred during tests with the pulse applied to the package input, but the damage occurred at lower voltages. ESD pulses with peak voltages as low as 250 volts produced arcs from the lid to the input bond wires, resulting in degraded inputs.

Research Organization:
Sandia National Labs., Albuquerque, NM (USA)
DOE Contract Number:
AC04-76DP00789
OSTI ID:
5750911
Report Number(s):
SAND-83-1045C; CONF-8309162-1; ON: DE84000138
Resource Relation:
Conference: 5. annual EOS/ESD symposium, Las Vegas, NV, USA, 27 Sep 1983; Other Information: Portions are illegible in microfiche products
Country of Publication:
United States
Language:
English