Pipeline multiprocessor architecture for high speed cell image analysis

Conference · Sat Oct 01 00:00:00 EDT 1983

OSTI ID:5294982

Castleman, K R; Price, K H; Eskenazi, R; Ovadya, M M; Navon, M A

A pipeline multiple-microprocessor architecture for high-speed digital image processing is being developed. The goal is a compact, fast, and low-cost pap smear analyzer for cervical cancer detection. Each processor communicates with one or two upstream processors and from one to 13 downstream processors via shared memory. Each of the identical pipeline modules (PC boards) has a Motorla MC6809 microprocessor with a 2 megabyte memory management unit, two 64kbyte dual-port image memories (shared with upstream processors) and one 64kbyte dual-port program memory (shared with a host computer). Intermodule communication is achieved by ribbon cables connected to connectors at the top of the boards. This allows considerable flexibility in configuring the system. This architecture should facilitate efficient (fast, low-cost) implementations of complex single-purpose image processing systems.

• OSTI ID: 5294982
• Resource Relation: Conference: Sponsored by IEEE, Pasadena, CA, USA, 12 Oct 1983
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
ARCHITECTURE
COMMUNICATIONS
DATA-FLOW PROCESSING
IMAGE PROCESSING
USES
PROCESSING
PROGRAMMING
990200* - Mathematics & Computers